The present disclosure relates to interconnect structures of semiconductor integrated circuits, specifically relates to interconnect structures of power supply interconnects of the semiconductor integrated circuits.
If the power supply interconnects of the semiconductor integrated circuits are formed using two or more interconnect layers, the power supply interconnects have, in general, an interconnect structure in the shape of a mesh or similar to a mesh. In this case, to reduce a noise effect on a signal interconnect, the signal interconnect is sealed by power supply interconnects located in a lateral direction and a vertical direction of the signal interconnect (see, for example, Japanese Patent Publication No. 2005-332903).
FIG. 14 shows an example arrangement of signal interconnects and power supply interconnects in a conventional semiconductor device. In FIG. 14, the reference character “200” represents a memory core; “201” represents an nth layer power supply interconnect for the memory core; “202” represents an nth layer signal interconnect; “203” represents an (n+1)th layer power supply interconnect for the memory core; “204” represents an (n+1)th layer signal interconnect; and “205” represents a contact between interconnect layers. In the conventional semiconductor device shown in FIG. 14, power supply interconnects are arranged in the shape of a mesh, using an nth layer and an (n+1)th layer. Each of the power supply interconnects extends one-dimensionally in a predetermined direction in each of the nth layer and the (n+1)th layer.